run_vtr_flow

This script runs the VTR flow for a single benchmark circuit and architecture file.

The script is located at:

$VTR_ROOT/vtr_flow/scripts/run_vtr_flow.py

Basic Usage

At a minimum run_vtr_flow.py requires two command-line arguments:

run_vtr_flow.py <circuit_file> <architecture_file>

where:

  • <circuit_file> is the circuit to be processed

  • <architecture_file> is the target FPGA architecture

Note

The script will create a ./temp directory, unless otherwise specified with the -temp_dir option. The circuit file and architecture file will be copied to the temporary directory. All stages of the flow will be run within this directory. Several intermediate files will be generated and deleted upon completion. Users should ensure that no important files are kept in this directory as they may be deleted.

Output

The standard out of the script will produce a single line with the format:

<architecture>/<circuit_name>...<status>

If execution completed successfully the status will be ‘OK’. Otherwise, the status will indicate which stage of execution failed.

The script will also produce an output files (*.out) for each stage, containing the standout output of the executable(s).

Advanced Usage

Additional optional command arguments can also be passed to run_vtr_flow.py:

run_vtr_flow.py <circuit_file> <architecture_file> [<options>] [<vpr_options>]

where:

  • <options> are additional arguments passed to run_vtr_flow.py (described below),

  • <vpr_options> are any arguments not recognized by run_vtr_flow.py. These will be forwarded to VPR.

For example:

run_vtr_flow.py my_circuit.v my_arch.xml -track_memory_usage --pack --place

will run the VTR flow to map the circuit my_circuit.v onto the architecture my_arch.xml; the arguments --pack and --place will be passed to VPR (since they are unrecognized arguments to run_vtr_flow.py). They will cause VPR to perform only packing and placement.

# Using the Yosys conventional Verilog parser
./run_vtr_flow <path/to/Verilog/File> <path/to/arch/file>

Running the VTR flow with the default configuration using the Yosys standalone front-end. The parser for these runs is considered the Yosys conventional Verilog/SystemVerilog parser (i.e., read_verilog -sv), as the parser is not explicitly specified.

# Using the Yosys-Slang plugin for Yosys, otherwise the Yosys conventional Verilog parser
./run_vtr_flow <path/to/SystemVerilog/File> <path/to/arch/file> -parser slang

Will run the VTR flow (default configuration) with Yosys-Slang plugin for Yosys frontend using Parmys plugin as partial mapper. The Yosys-Slang SystemVerilog parser supports the (i.e., read_slang) command. Yosys-Slang builds on top of the slang library to provide comprehensive SystemVerilog support. Enable the Yosys-Slang plugin with the -DSLANG_SYSTEMVERILOG=ON compile flag while building the VTR project with yosys as a frontend.

Note

Yosys-Slang is currently experimental.

# Using the Parmys (Partial Mapper for Yosys) plugin as partial mapper
./run_vtr_flow <path/to/Verilog/File> <path/to/arch/file>

Will run the VTR flow (default configuration) with Yosys frontend using Parmys plugin as partial mapper. To utilize the Parmys plugin, the -DYOSYS_PARMYS_PLUGIN=ON compile flag should be passed while building the VTR project with Yosys as a frontend.

# Using the Parmys (Partial Mapper for Yosys) plugin as partial mapper with include files
./run_vtr_flow <path/to/Verilog/File> <path/to/arch/file> -include <path/to/include/directory>/*.v*

Will run the VTR flow (default configuration) with Yosys frontend using Parmys plugin as partial mapper. In addition to the main circuit passed in with the architecture, it will also pass in every HDL file with the specified file type within the include directory.

Detailed Command-line Options

Note

Any options not recognized by this script is forwarded to VPR.

-starting_stage <stage>

Start the VTR flow at the specified stage.

Accepted values:

  • odin

  • parmys

  • abc

  • scripts

  • vpr

Default: parmys

-ending_stage <stage>

End the VTR flow at the specified stage.

Accepted values:

  • odin

  • parmys

  • abc

  • scripts

  • vpr

Default: vpr

-include <path_to_file(s)>/*.<file_type(s)>

List of include files to a benchmark circuit (pass to VTR frontends as a benchmark design set).

Include files can be any file supported by yosys+parmys (normally .v or .vh files).

The include directory should not contain the circuit passed in with the architecture.

-power

Enables power estimation.

See Power Estimation

-cmos_tech <file>

CMOS technology XML file.

See Technology Properties

-delete_intermediate_files

Delete intermediate files (i.e. .dot, .xml, .rc, etc)

-delete_result_files

Delete result files (i.e. VPR’s .net, .place, .route outputs)

-track_memory_usage

Record peak memory usage and additional statistics for each stage.

Note

Requires /usr/bin/time -v command. Some operating systems do not report peak memory.

Default: off

-limit_memory_usage

Kill benchmark if it is taking up too much memory to avoid slow disk swaps.

Note

Requires ulimit -Sv command.

Default: off

-timeout <float>

Maximum amount of time to spend on a single stage of a task in seconds.

Default: 14 days

-temp_dir <path>

Temporary directory used for execution and intermediate files. The script will automatically create this directory if necessary.

Default: ./temp

-valgrind

Run the flow with valgrind while using the following valgrind options:

  • –leak-check=full

  • –errors-for-leak-kinds=none

  • –error-exitcode=1

  • –track-origins=yes

-min_hard_mult_size <int>

Tells Parmys/ODIN II the minimum multiplier size (in bits) that should be implemented using a hard multiplier (if available). Smaller multipliers will be implemented using soft logic.

Default: 3

-min_hard_adder_size <int>

Tells Parmys/ODIN II the minimum adder size (in bits) that should be implemented using hard adders (if available). Smaller adders will be implemented using soft logic.

Default: 1

-adder_cin_global

Tells Parmys/ODIN II to connect the first cin in an adder/subtractor chain to a global gnd/vdd net. Instead of creating a dummy adder to generate the input signal of the first cin port of the chain.

-odin_xml <path_to_custom_xml>

Tells VTR flow to use a custom ODIN II configuration value. The default behavior is to use the vtr_flow/misc/basic_odin_config_split.xml. Instead, an alternative config file might be supplied; compare the default and vtr_flow/misc/custom_odin_config_no_mults.xml for usage scenarios. This option is needed for running the entire VTR flow with additional parameters for ODIN II that are provided from within the .xml file.

-use_odin_simulation

Tells ODIN II to run simulation.

-top_module <TOP_MODULE>

Specifies the name of the module in the design that should be considered as top

-yosys_script <YOSYS_SCRIPT>

Supplies Parmys(Yosys) with a .ys script file (similar to Tcl script), including the synthesis steps.

Default: None

-parser <PARSER>

Specify a parser for the Yosys synthesizer [default (Verilog-2005), slang (SystemVerilog)]. The script uses the default conventional Verilog parser if this argument is not used.

Default: default

Note

Yosys-Slang is a Yosys plugin that is built on top of the slang library to provide comprehensive SystemVerilog support. It supports the read_slang command, used with the -C command-line option to read include-files from a text file containing include-file names. It is used to read SystemVerilog files directly in Yosys. For more information on Yosys-Slang, see [Yosys-Slang]

Note

Parmys is a Yosys plugin which provides intelligent partial mapping features (inference, binding, and hard/soft logic trade-offs) from Odin-II for Yosys. For more information on available parameters see the Parmys plugin page.