Physical Types

These types are used to capture user’s intended architecture specification.

struct t_arch

Public Functions

const t_grid_def &grid_layout() const: Returns the grid layout specified by the —device command-line option.

Public Members

mutable vtr::string_internment strings: Stores unique strings used as key and values in <metadata> tags, i.e. implements a flyweight pattern to save memory.

std::string architecture_id: Secure hash digest of the architecture file to uniquely identify this architecture.

bool tileable: Whether the routing architecture is tileable.

bool perimeter_cb: Allow connection blocks to appear around the perimeter programmable block.

bool shrink_boundary: Remove all the routing wires in empty regions.

bool through_channel: Allow routing channels to pass through multi-width and multi-height programmable blocks

bool opin2all_sides: Allow each output pin of a programmable block to drive the routing tracks on all the sides of its adjacent switch block

bool concat_wire: Whether the routing architecture has concat wire For further detail, please refer to documentation

bool concat_pass_wire: Whether the routing architecture has concat pass wire For further detail, please refer to documentation

int sub_fs: Connectivity parameter for pass tracks in each switch block.

e_switch_block_type sb_sub_type: Connecting type for pass tracks in each switch block.

std::vector<t_arch_switch_inf> switches: Contains information from all switch types defined in the architecture file.

std::vector<t_direct_inf> directs: Contains information about all direct chain connections in the architecture.

std::vector<t_grid_def> grid_layouts: Set of potential device layouts.

t_noc_inf *noc = nullptr: Stores NoC-related architectural information when there is an embedded NoC.

std::vector<t_vib_grid_def> vib_grid_layouts: VIB grid layouts.

std::vector<t_scatter_gather_pattern> scatter_gather_patterns: Stores information for scatter-gather patterns that can be used to define some of the rr-graph connectivity.

struct t_arch_switch_inf

Lists all the important information about a switch type read from the architecture file.

Public Members

float R = 0.: Equivalent resistance of the buffer/switch.

float Cin = 0.: Input capacitance.

float Cout = 0.: Output capacitance.

float Cinternal = 0.

The internal capacitance.

Since multiplexers and tristate buffers are modeled as a parallel stream of pass transistors feeding into a buffer, we would expect an additional “internal capacitance to arise when the pass transistor is enabled and the signal must propagate to the buffer. See diagram of one stream below:

Pass Transistor
     |
   -----
   -----      Buffer
  |     |       |\

—— —-—| \ –— | | | / | ===== ===== |/ ===== ===== ===== ===== | | | Input C Internal C Output C

float mux_trans_size = 1.: The area of each transistor in the segment’s driving mux measured in minimum width transistor units.

float buf_size = 0.: The area of the buffer. If set to zero, area should be calculated from R.

struct t_segment_inf

Lists all the important information about a certain segment type. Only used if the route_type is DETAILED. [0 .. det_routing_arch.num_segment].

Public Members

std::string name: The name of the segment type.

int frequency: brief ratio of tracks which are of this segment type.

int length: Length (in clbs) of the segment.

short arch_wire_switch: Index of the switch type that connects other wires to this segment. Note that this index is in relation to the switches from the architecture file, not the expanded list of switches that is built at the end of build_rr_graph.

short arch_opin_switch: Index of the switch type that connects output pins to this segment. Note that this index is in relation to the switches from the architecture file, not the expanded list of switches that is built at the end of build_rr_graph.

short arch_wire_switch_dec = ARCH_FPGA_UNDEFINED_VAL: Same as arch_wire_switch but used only for decremental tracks if it is specified in the architecture file. If -1, this value was not set in the architecture file and arch_wire_switch should be used for “DEC_DIR” wire segments.

short arch_opin_switch_dec = ARCH_FPGA_UNDEFINED_VAL: Same as arch_opin_switch but used only for decremental tracks if it is specified in the architecture file. If -1, this value was not set in the architecture file and arch_opin_switch should be used for “DEC_DIR” wire segments.

short arch_inter_die_switch = ARCH_FPGA_UNDEFINED_VAL: Index of the switch type that connects output pins (OPINs) to this segment from another die (layer). Note that this index is in relation to the switches from the architecture file, not the expanded list of switches that is built at the end of build_rr_graph.

float frac_cb: The fraction of logic blocks along its length to which this segment can connect. (i.e. internal population).

float frac_sb: The fraction of the length + 1 switch blocks along the segment to which the segment can connect. Segments that aren’t long lines must connect to at least two switch boxes.

float Rmetal: The resistance of a routing track, per unit logic block length.

float Cmetal: The capacitance of a routing track, per unit logic block length.

e_parallel_axis parallel_axis: Defines what axis the segment is parallel to. See e_parallel_axis comments for more details on the values.

std::vector<bool> cb: A vector of booleans indicating whether the segment can connect to a logic block.

std::vector<bool> sb: A vector of booleans indicating whether the segment can connect to a switch block.

bool is_bend: This segment is bend or not.

std::vector<int> bend: The bend type of the segment, “-“-0, “U”-1, “D”-2 For example: bend pattern <- - U ->; corresponding bend: [0,0,1,0].

std::vector<int> part_len: Divide the segment into several parts based on bend position. For example: length-5 bend segment: <- - U ->; Corresponding part_len: [3,2].

int seg_index: The index of the segment as stored in the appropriate Segs list. Upon loading the architecture, we use this field to keep track of the segment’s index in the unified segment_inf vector. This is useful when building the rr_graph for different Y & X channels in terms of track distribution and segment type.

enum SegResType res_type = SegResType::GENERAL

Determines the routing network to which the segment belongs. Possible values are:

GENERAL: The segment is part of the general routing resources.
GCLK: The segment is part of the global routing network. For backward compatibility, this attribute is optional. If not specified, the resource type for the segment is considered to be GENERAL.

struct t_physical_tile_loc

Describes The location of a physical tile.

Param x:: The x location of the physical tile on the given die
Param y:: The y location of the physical tile on the given die
Param layer_num:: The die number of the physical tile. If the FPGA only has one die, or the physical tile is located on the base die, layer_num is equal to zero. If the physical tile is location on the die immediately above the base die, the layer_num is 1 and so on.

Friends

inline friend bool operator<(const t_physical_tile_loc &lhs, const t_physical_tile_loc &rhs)

Comparison operator for t_physical_tile_loc.

Tiles are ordered first by layer number, then by x, and finally by y.

struct t_sub_tile

Describes the possible placeable blocks within a physical tile type.

Heterogeneous blocks:

The sub tile allows to have heterogeneous blocks placed at the same grid location. Heterogeneous blocks are blocks which do not share either the same functionality or the IO interface, but do share the same (x, y) grid location. For each heterogeneous block type than, there should be a corresponding sub tile to enable its placement within the physical tile.

For further information there is a tutorial on the VTR documentation page.

Equivalent sites:

Moreover, the same sub tile enables to allow the placement of different implementations of a logical block. This means that two blocks that have different internal functionalities, but the IO interface of one block is a subset of the other, they can be placed at the same sub tile location within the physical tile. These two blocks can be identified as equivalent, hence they can belong to the same sub tile.

Public Functions

const t_physical_tile_port *get_port(std::string_view port_name): Returns the physical tile port given the port name and the corresponding sub tile.

const t_physical_tile_port *get_port_by_pin(int pin) const: Returns the physical tile port given the pin name and the corresponding sub tile.

Public Members

t_capacity_range capacity: >List of netlist blocks (t_logical_block) that one could >place within this sub tile.

t_class_range class_range

>Indicates the total number of sub tile instances of this type placeable at a >physical location. >E.g.: capacity can range from 4 to 7, meaning that there are four placeable sub tiles

at a physical location, and compatible netlist blocks can be placed at sub_tile indices ranging from 4 to 7.

struct t_layer_def

Public Members

std::vector<t_grid_loc_def> loc_defs: List of block location definitions for this layer specification.

std::vector<t_interposer_cut_inf> interposer_cuts: List of interposer cuts in this layer.

struct t_grid_def